Today I did play around with Xilinx Vivado a little, take a look at an example project, look at the synthesis and implementation options (not much new) &cetera.
The last couple of years I have been exclusively working with Xilinx ISE 14.4, mostly avoiding the Project Navigator, but instead using the command line tools like xst, ngdbuild, par, trce and so on directly (from a Makefile). To get some feeling for what awaits me when migrating an existing VHDL project from ISE to Vivado I did create a new Vivado project and imported the code of an existing VHDL project. While doing this I stumbled over a few things that Vivado handles more correctly and a few other things which Vivado, for unknown reasons, does no longer handle as well as ISE (or fails to handle at all).
I am comparing ISE 14.4 against Vivado 2015.3 here!