For a long time I did not like when people declare their ports like this in VHDL:
entity example is port ( foo : in std_logic; bar : out std_logic; glarp : inout std_logic );
I was fine with vertical alignment along the colons, but the additional whitespace after the in/out keywords just looked horrific to me.
The same goes, to a less extent, for Verilog multibit wires/registers:
module example ( input wire [7:0] foo, output reg bar )
This all changed when I found out about column mode editing in Notepad++.