Category: asic

First Steps with Google SkyWater PDK – Free Open Source Silicon for Everyone

For a while now Google has been collaborating with SkyWater Technology to create what many refer to as free and open source silicon (FOSSi). The project gained traction in 2020 and is continuing to gain momentum.
The proclaimed goal is to bring chip design to the masses and enable everyone from academia, industry and makers to create their own computer chips. If this plan succeeds it would mean a considerable shift in the chip industry which traditionally is very secretive and dominated by just a few big corporations and their partners, connected by a opaque web of interdependencies. (Surely Google counts as the underdog in comparison *cough*)

Getting Started with Magic VLSI

Magic VLSI – or just Magic – is a free and open source VLSI layout software. Simply put Magic allows you to draw the mask layers used in a semiconductor facrication process. The Magic software is another “Berkeley Child” (like BSD and others) and first came into existence in the 1980s. Magic is still under active development as of late 2019.

Some Linux distributions offer a pre-build package for Magic from their package repository. Most often these packages are outdated and therefor it is best to build Magic from the sources.

Interesting Read about IP-XACT

In case you are interested in FPGA/ASIC design and/or HDL coding you may find this blog entry about IP-XACT worthy of reading.

ASIC Design Tutorials And Why They’re Rare

Most information about ASIC technologies and semiconductor processes are not public and only supplied under strict NDAs. Therefor only very few useful tutorials about ASIC design and layout exist. Though few in number they do exist. Here are a few noteworthy ones. I did not read through them completely but only briefly skipped through them and thought they looked promising at first glance.

http://www.designinganalogchips.com/
https://www.mics.ece.vt.edu/ICDesign/Tutorials/Overview/index.html
https://web.archive.org/web/*/Designing%20Analog%20Chips

VLSI tools in 500 LOC or Longing for Attention

My VLSI tools take a chip from conception through testing. Perhaps 500 lines of source code. Cadence, Mentor Graphics do the same, more or less. With how much source/object code?

– Chuck Moore, the inventor of Forth –

Now, I’ve seen chip design tools by the likes of Cadence and Mentor Graphics. Astronomically costly licenses. Geological run times. And nobody quite knows what they do.

– http://yosefk.com/blog/my-history-with-forth-stack-machines.html –

Testbench != Simulation

There is a difference between testbench files and simulation files:
Testbench files are independent of the simulator and comparable tools. They include testbench configuration files, test case descriptions or stimuli and golden reference output files.

Simulation files are setup and command files for a simulator or similar vendor tool. Related configuration files include waveform settings and simulation scripts.

A project’s folder structure should also draw this distinction to keep simulator/vendor independent files separate. Log files and results should therefor be put in an output folder alongside the testbench files.

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