For quite a while I have followed the RISC-V ISA with growing intereset. Now that RISC-V is becoming more and more popular and catching a lot of public attention, it is time to get my hands dirty with some low level RISC-V assembly coding.
Category: coding
When tasked with the implementation of a rather complex function, e.g. a polynomial of higher order, the resource utilization quickly shoots through the roof if implemented straight forward (also called the naïve implementation).
To avoid this it is often easier, simpler and faster to use a lookup table (LUT) solution.
For the STM32 family of microcontrollers a number of different support libaries are available: Cortex Microcontroller Software Interface Standard (CMSIS), Standard Peripheral Library (SPL), Hardware Abstraction Layer (HAL).
For a long time I did not like when people declare their ports like this in VHDL:
entity example is
port (
foo : in std_logic;
bar : out std_logic;
glarp : inout std_logic
);
I was fine with vertical alignment along the colons, but the additional whitespace after the in/out keywords just looked horrific to me.
The same goes, to a less extent, for Verilog multibit wires/registers:
module example ( input wire [7:0] foo, output reg bar )
This all changed when I found out about column mode editing in Notepad++.
On occasion it can be super useful to have the ternary operator ? : at hand. Many programming languages like C have it and – without proof – I dare claim that it is much appreciated by many coders out there.
There are often multiple choices when we are looking for a software tool to do <something>. Some of the possible softwares may be quite archaic, have been around for decades and were used for many different tasks and in many projects throughout their lifetime. Others may be the latest newcomers, have not even hit version 1.0 yet, are built on top of brand new frameworks, libraries and APIs, and come with a modern look-and-feel.
A nice read about Semantic Versioning.
Try to avoid
use work.mypack.all;
This can cause name conflicts, e.g. if two packages define a type of the same name. It is far less likely to have conflicting type and package names. Even if so, its a hell lot easier to fix, e.g. by renaming one of the packages.
This problem may be found when integrating 3rd party code as a black box (i.e. not knowing or caring whats inside).
Therefor choose package names as descriptive as possible, while keeping them reasonably short.
I am aware that name conflict are unlikely in VHDL. Very few widely used packages exist and the whole library concept is omitted by most developers. I bet 99% of digital design engineers never ever used a different library than work for their packages. But that’s no reason to ignore best practices.
What is a HDL?
A hardware description language (HDL) is a computer language used to describe the structure and behavior of digital (and sometimes analog) electronic circuits. A HDL may look quite similar to a traditional programming language and indeed will behave similar as well in some aspects, however in other aspects there are important differences that one must be aware of when writing HDL code.
This article is meant to give an extremely brief overview of HDLs, their origins, what’s so special about them and what state of the art HDLs of today can offer.
