vhdl – bananatronics.org

Getting Started with GHDL

On 2019-11-04

If you haven’t heard of GHDL, it is *the* free open-source VHDL simulator out there.
GHDL stand for “G Hardware Description Language” (the G is without meaning). GHDL is mainly implemented in Ada and can be build with different backends: mcode, LLVM and GCC. The different backends provide different performance levels and vary in build complexity. I recommend LLVM since it performs well and is still quite straight forward to build. Building GHDL from latest sources from its github project is probably the best way to go.

Despite its free nature GHDL provides very good support for all major VHDL-LRM releases: VHDL-1987/1993/200X/2008(partial). Unfortunately GHDL is a pure VHDL simulator, so there is no support for Verilog at all. This is understandable as there are already some very good simulators for Verilog out there.

Anlogic TANG PriMER dev board

By andrsmllr

On 2019-09-01

In 101, electronics, fpga, risc-v, software, tutorial/howto, verilog, vhdl

Recently I purchased a Sipeed TANG PriMER development board featuring an Anlogic EG4S20 FPGA (codenamed Eagle S20). The only reason I bought the board was to see what Anlogic FPGAs are capable of, since I had never heard of that FPGA vendor before. No need to think twice when the board costs less than 20$.

Clock Enables vs. Multiple Clocks

By andrsmllr

On 2019-05-04

In fpga, tutorial/howto, verilog, vhdl

Introduction

In advanced FPGA systems which require different clock frequencies for different parts of the design, there is often a shortage of global clock buffers. Often several of the clocks are related (see below) and it becomes possible to use a single clock plus several clock enable signals, instead of several dedicated clocks. This article tries to shed some light on the impact these two alternatives can have on an FPGA system.

Notepad++ Column Mode

By andrsmllr

On 2018-02-23

In coding, find, verilog, vhdl

For a long time I did not like when people declare their ports like this in VHDL:

entity example is
  port (
    foo    : in        std_logic;
    bar    : out     std_logic;
    glarp : inout std_logic
  );

I was fine with vertical alignment along the colons, but the additional whitespace after the in/out keywords just looked horrific to me.
The same goes, to a less extent, for Verilog multibit wires/registers:

module example (
  input  wire [7:0] foo,
  output reg        bar
)

This all changed when I found out about column mode editing in Notepad++.

Simulation Advice

By andrsmllr

On 2018-01-19

In fpga, verification, verilog, vhdl

Here is some general advice for simulation of HDL code. No respect is paid to verification methodologies like UVM or OSVVM. Most of it is obvious, but it helps my memory when I write these things down.

Use assert statements to catch error events. Your eyes can miss even the most obvious error when scanning over some simulation waveforms after a long day in front of the screen.
Use log files and/or report statements to save information about the status and progress of simulation, errors or any other noteworthy event. This will speed up the task of locating events of interest and will allow you to do text searches over those files.
Use colors, the right radix for numbers and hierarchical structure in your waveform viewer for optimal data representation. Unless you prefer to look at heaps of green lines with loads of 0’s and 1’s around them.
Save your simulator/waveform settings. At some point you will come back and won’t have to repeat the tedious task of setting up a neat waveform view. The simulator/waveform settings should also go into the repository (separate folder for each simulator), but it’s a matter of taste.

Ternary operator for VHDL

By andrsmllr

On 2018-01-04

In coding, fpga, vhdl

On occasion it can be super useful to have the ternary operator ? : at hand. Many programming languages like C have it and – without proof – I dare claim that it is much appreciated by many coders out there.

Differences in the Handling of VHDL Code between Vivado and ISE

By andrsmllr

On 2017-12-19

In fpga, vhdl

Today I did play around with Xilinx Vivado a little, take a look at an example project, look at the synthesis and implementation options (not much new) &cetera.
The last couple of years I have been exclusively working with Xilinx ISE 14.4, mostly avoiding the Project Navigator, but instead using the command line tools like xst, ngdbuild, par, trce and so on directly (from a Makefile). To get some feeling for what awaits me when migrating an existing VHDL project from ISE to Vivado I did create a new Vivado project and imported the code of an existing VHDL project. While doing this I stumbled over a few things that Vivado handles more correctly and a few other things which Vivado, for unknown reasons, does no longer handle as well as ISE (or fails to handle at all).
I am comparing ISE 14.4 against Vivado 2015.3 here!

Testbench != Simulation

By andrsmllr

On 2017-09-12

In asic, fpga, Uncategorized, verification, verilog, vhdl

There is a difference between testbench files and simulation files:
Testbench files are independent of the simulator and comparable tools. They include testbench configuration files, test case descriptions or stimuli and golden reference output files.

Simulation files are setup and command files for a simulator or similar vendor tool. Related configuration files include waveform settings and simulation scripts.

A project’s folder structure should also draw this distinction to keep simulator/vendor independent files separate. Log files and results should therefor be put in an output folder alongside the testbench files.

VHDL package use

By andrsmllr

On 2017-09-11

In coding, fpga, vhdl

Try to avoid

use work.mypack.all;

This can cause name conflicts, e.g. if two packages define a type of the same name. It is far less likely to have conflicting type and package names. Even if so, its a hell lot easier to fix, e.g. by renaming one of the packages.
This problem may be found when integrating 3rd party code as a black box (i.e. not knowing or caring whats inside).
Therefor choose package names as descriptive as possible, while keeping them reasonably short.

I am aware that name conflict are unlikely in VHDL. Very few widely used packages exist and the whole library concept is omitted by most developers. I bet 99% of digital design engineers never ever used a different library than work for their packages. But that’s no reason to ignore best practices.

What Is a Hardware Description Language Anyway?

By andrsmllr

On 2017-09-11

In coding, fpga, verilog, vhdl

What is a HDL?

A hardware description language (HDL) is a computer language used to describe the structure and behavior of digital (and sometimes analog) electronic circuits. A HDL may look quite similar to a traditional programming language and indeed will behave similar as well in some aspects, however in other aspects there are important differences that one must be aware of when writing HDL code.

This article is meant to give an extremely brief overview of HDLs, their origins, what’s so special about them and what state of the art HDLs of today can offer.

Category: vhdl

Introduction

What is a HDL?