For a long time I did not like when people declare their ports like this in VHDL:

entity example is
  port (
    foo    : in        std_logic;
    bar    : out     std_logic;
    glarp : inout std_logic

I was fine with vertical alignment along the colons, but the additional whitespace after the in/out keywords just looked horrific to me.
The same goes, to a less extent, for Verilog multibit wires/registers:

module example (
  input  wire [7:0] foo,
  output reg        bar

This all changed when I found out about column mode editing in Notepad++.

To enter column mode editing the Alt-key must be held while selecting text with the mouse. Since I know about this feature the vertical alignment of in/out keywords and port types makes perfect sense.Only with the port types vertically aligned can I use column mode editing to quickly change the type of a bunch of ports.
Column mode editing has even more to offer, check out Edit > Column Editor in Notepad++’s menu bar.


Of course column mode editing can not replace all the super magic features of high-end (and high-price) IDEs like Sigasi. But it is a great help for all those who do not have access to expensive IDEs.