At some point we all want to store Docker images and volumes on a different drive, to avoid the system drive being filled up as the volumes grow. Here’s how.
For a while now Google has been collaborating with SkyWater Technology to create what many refer to as free and open source silicon (FOSSi). The project gained traction in 2020 and is continuing to gain momentum.
The proclaimed goal is to bring chip design to the masses and enable everyone from academia, industry and makers to create their own computer chips. If this plan succeeds it would mean a considerable shift in the chip industry which traditionally is very secretive and dominated by just a few big corporations and their partners, connected by a opaque web of interdependencies. (Surely Google counts as the underdog in comparison *cough*)
Wireguard is a modern VPN protocol allowing secure and confidential communication between a network of peers. Wireguard is based on the concept of private-public key cryptography and a number of other modern cryptographic algorithms. Have a look at the wireguard white paper for more details.
Since Linux kernel version 5.6 (late March 2020) wireguard is an integral part of the Linux kernel. That means Linux distributions using a kernel >= 5.6 do not need to install any additional packages in order to support wireguard.
The Longan Nano is a new contestor in the area of affordable RISC-V development boards. The Longan Nano’s form factor and price puts it up against the Arduino Nano and all other varieties of STM32-based “nano boards”, which can be found abundantly on Ebay and AliExpress.
Working on the command line in a Linux shell can be tricky at times. A frequent source of frustration is that tasks which are trivial with a graphical desktop environment can be seemingly much more difficult to achieve on the command line. For example switching between multiple running applications only requires one or two mouse clicks on a graphical desktop, but demands more arcane knowledge to do it on the command line.
In advanced FPGA systems which require different clock frequencies for different parts of the design, there is often a shortage of global clock buffers. Often several of the clocks are related (see below) and it becomes possible to use a single clock plus several clock enable signals, instead of several dedicated clocks. This article tries to shed some light on the impact these two alternatives can have on an FPGA system.