On occasion it can be super useful to have the ternary operator ? : at hand. Many programming languages like C have it and – without proof – I dare claim that it is much appreciated by many coders out there.
In VHDL there is no such thing. Instead a VHDL developer must always bring out the big gun and apply our beloved if-then-else(-endif) statement.
if (fifo_empty = '1') then read_fifo <= '0'; else read_fifo <= '1'; end if;
However, it would be really nice to have a ternary short-hand operator available instead sometimes.
Here’s a surrogate for the ternary operator which works without changing the VHDL LRM. It is a simple function ite, which is short for if-then-else 🙂 The function does nothing more but wrap an if-then-else statement. How ingenious of me.
function ite(b: boolean; x, y: integer) return integer is begin if (b) then return x; else return y; end if; end function ite;
Of course this function will only work for integer arguments, but it can easily be overloaded for other data types (I smell an application for a VHDL-2008 type generic).
P.S.: Verilog has a ternary operator.